1. Technological Field
Embodiments discussed herein relate to a semiconductor memory device, and more specifically, to a semiconductor memory device including a cell array in which static random access memory (SRAM) cells are arranged
2. Description of the Related Art
In general, a SRAM cell includes two inverters each made of a positive-channel metal-oxide semiconductor (PMOS) transistor and a negative-channel metal-oxide semiconductor (NMOS) transistor, and an input terminal and an output terminal of one of the two inverters are connected to an output terminal and an input terminal of the other inverter, respectively. Moreover, there has been known a configuration to provide the SRAM cell with a read port in addition to a write port in order to accelerate data reading out of this SRAM cell or to execute data reading in parallel with data writing. As a configuration of the read port, there has been known one including a read transfer transistor and a read driver transistor connected to the input terminal of any of the two inverters in the SRAM cell. In this case, each SRAM cell includes eight MOS transistors in total.
Meanwhile, as another configuration of the read port, there has also been known one including two pairs of read driver transistors and read transfer transistors respectively connected to the input terminals of the two inverters in the SRAM cell. In this case, each SRAM cell includes ten MOS transistors in total.
The cell size has been reduced along with a progress in scaling in recent years. In general, the value of a cell current to flow through a transistor is reduced by scaling down the transistor. However, it is preferable to feed a large cell current to a read transfer transistor in order to improve a readout characteristic of a read port. This has made it difficult to reduce the cell size of the read transfer transistor.